The present inventive concept relates to integrated circuit devices and related methods of operation.
Advances in semiconductor manufacturing technologies continue to improve the integrity and decrease the size of semiconductor devices. However, providing such advances in semiconductor devices fabrication may be expensive, for example, due to costs that may be required to upgrade the facilities and/or equipment used in wafer fabrication, in addition to research-related costs. For instance, in semiconductor memory devices, upgrading a fabrication process used to produce a 64 megabit (Mb) dynamic random access memory (DRAM) devices to allow for production of 256 Mb DRAM devices may involve significant costs.
Semiconductor device manufacturers have introduced fabrication methods whereby a plurality of semiconductor chips are placed into one package. In particular, two or more semiconductor chips may be arranged or “stacked” one on top of the other, to provide a stacked multi-chip package (MCP). The stacking of multiple semiconductor chips in one package may improve the integrity and/or performance of semiconductor devices without requiring the fabrication of new wafer. For example, a 256 Mb DRAM device can be fabricated by assembling four 64 Mb DRAM semiconductor memory chips in the same package.
FIG. 1A illustrates an example of a stacked semiconductor package 100 including second, third, and fourth semiconductor chips 102-104 that are stacked offset on a first semiconductor chip 101, such that a portion of each of the semiconductor chips 101-104 is exposed. A bonding wire 112 electrically connects an exposed pad on a substrate 10 to the first semiconductor chip 101, to the second semiconductor chip 102, to the third semiconductor chip 103, and to the fourth semiconductor chip 104 in a step-by-step manner, from the bottommost chip 101 to the topmost chip 104.
However, the more semiconductor chips that are stacked in a package, the greater the signal delay may be among the chips in the package. FIG. 1B illustrates a package 100′ including eight chips 101-108 in a chip stack, where a bonding wire 112′ electrically connects the exposed pad on the substrate 10 to each of the chips 101-108. Accordingly, if the time required to transmit a signal from the substrate 10 to the first chip 101 in the stack is ‘t’, the time required to transmit a signal to the eighth chip 108 in the stack may be ‘8t’. Therefore, providing additional chips in a package may increase the signal delay time among the offset-stacked semiconductor chips.